20UPGFC0134184 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 66f5fdb4c5fb563270c414db

This Revision: 66f5fdb4c5fb563270c414dc

Latest Revision: 673686b056f39c8f40b1e7bc

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA9
SldoTrimD11

Parameter

ADCcalPar
  • 0.83
  • 0.179
  • 10000.0
Name0x20c28
ChipId13
InjCap7.795
NfDSLDO1.252463410263939
NfASLDO1.2543489834360193
NfACB1.2512920693540102
VcalPar
  • 15.968
  • 0.193
IrefTrim5
KSenseInA20806.12
KSenseInD21670.21
KSenseShuntA25759.958095238097
KSenseShuntD26829.78380952381
KShuntA1011.996
KShuntD1008.46

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA9
SldoTrimD11
Parameter
ADCcalPar
  • 0.83
  • 0.179
  • 10000.0
Name0x20c28
ChipId13
InjCap7.795
NfDSLDO1.252463410263939
NfASLDO1.2543489834360193
NfACB1.2512920693540102
VcalPar
  • 15.968
  • 0.193
IrefTrim5
KSenseInA20806.12
KSenseInD21670.21
KSenseShuntA25759.958095238097
KSenseShuntD26829.78380952381
KShuntA1011.996
KShuntD1008.46