20UPGFC0134184 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 66f5fdb4c5fb563270c414db

This Revision: 69013285fb15341973b89db2

Latest Revision: 69013285fb15341973b89db2

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	9
SldoTrimD	11

Parameter

ADCcalPar	0.83 0.179 10000.0
Name	0x20c28
ChipId	13
InjCap	7.795
NfDSLDO	1.252463410263939
NfASLDO	1.2543489834360193
NfACB	1.2512920693540102
VcalPar	15.968 0.193
IrefTrim	5
KSenseInA	20806.12
KSenseInD	21670.21

KSenseShuntA	25759.958095238097
KSenseShuntD	26829.78380952381
KShuntA	1011.996
KShuntD	1008.46

PixelConfig

Diff from previous revision 690025f848ef83fad08046e5

No diff is present.