20UPGFC0146069 Chip Configuration

Stage: MODULE/FINAL_COLD

Branch: LP

Config: 6a2a05be3437adbb7d7455e7

This Revision: 6a2a0820a2083033ec8cd898

Latest Revision: 6a2a0820a2083033ec8cd898

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA8
SldoTrimD9

Parameter

ADCcalPar
  • 1.362
  • 0.18
  • 10000.0
InjCap7.55
KSenseInA21421.596
KSenseInD21539.937
Name0x23a95
ChipId13
NfDSLDO1.2581865653978896
NfASLDO1.2581151440765417
NfACB1.2574152151273297
VcalPar
  • 13.453
  • 0.193
IrefTrim13
KSenseShuntA22034.0
KSenseShuntD22155.0
KShuntA1010.744
KShuntD995.285

PixelConfig

Diff from previous revision 6a2a05be3437adbb7d7455e8

No diff is present.