20UPGFC0146069 Chip Configuration

Stage: MODULE/FINAL_WARM

Branch: LP

Config: 6a289374382a2f15c9189938

This Revision: 6a289374382a2f15c9189939

Latest Revision: 6a28c95266f3d07de10177c8

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	8
SldoTrimD	9

Parameter

ADCcalPar	1.362 0.18 10000.0
InjCap	7.55
KSenseInA	21421.596
KSenseInD	21539.937
Name	0x23a95
ChipId	13
NfDSLDO	1.2581865653978896
NfASLDO	1.2581151440765417
NfACB	1.2574152151273297
VcalPar	13.453 0.193
IrefTrim	13

KSenseShuntA	22034.0
KSenseShuntD	22155.0
KShuntA	1010.744
KShuntD	995.285

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	8
SldoTrimD	9

Parameter

ADCcalPar	1.362 0.18 10000.0
InjCap	7.55
KSenseInA	21421.596
KSenseInD	21539.937
Name	0x23a95
ChipId	13
NfDSLDO	1.2581865653978896
NfASLDO	1.2581151440765417
NfACB	1.2574152151273297
VcalPar	13.453 0.193
IrefTrim	13
KSenseShuntA	22034.0
KSenseShuntD	22155.0
KShuntA	1010.744
KShuntD	995.285