20UPGFC0146067 Chip Configuration

Stage: MODULE/FINAL_WARM

Branch: LP

Config: 6a289370382a2f15c918992b

This Revision: 6a289370382a2f15c918992c

Latest Revision: 6a28c78866f3d07de1017759

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	11
SldoTrimD	8

Parameter

ADCcalPar	1.5 0.184 10000.0
InjCap	7.954999999999999
KSenseInA	21399.677
KSenseInD	21602.599
Name	0x23a93
ChipId	12
NfDSLDO	1.2591562043031144
NfASLDO	1.2591133510817176
NfACB	1.2575134974829025
VcalPar	12.05 0.196
IrefTrim	8

KSenseShuntA	22011.0
KSenseShuntD	22220.0
KShuntA	992.484
KShuntD	990.713

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	11
SldoTrimD	8

Parameter

ADCcalPar	1.5 0.184 10000.0
InjCap	7.954999999999999
KSenseInA	21399.677
KSenseInD	21602.599
Name	0x23a93
ChipId	12
NfDSLDO	1.2591562043031144
NfASLDO	1.2591133510817176
NfACB	1.2575134974829025
VcalPar	12.05 0.196
IrefTrim	8
KSenseShuntA	22011.0
KSenseShuntD	22220.0
KShuntA	992.484
KShuntD	990.713