20UPGFC0141722 Chip Configuration

Stage: MODULE/FINAL_WARM

Branch: LP

Config: 6a28935ee4d82762eb8e958f

This Revision: 6a28935ee4d82762eb8e9590

Latest Revision: 6a28c6fa66f3d07de1017738

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	8
SldoTrimD	8

Parameter

ADCcalPar	4.957 0.19 10000.0
InjCap	7.686000000000001
KSenseInA	21134.913
KSenseInD	21446.654
Name	0x2299a
ChipId	15
NfDSLDO	1.2629717939282172
NfASLDO	1.2637859969915861
NfACB	1.2618576213151855
VcalPar	13.365 0.203
IrefTrim	11

KSenseShuntA	21739.0
KSenseShuntD	22059.0
KShuntA	1004.329
KShuntD	997.911

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	8
SldoTrimD	8

Parameter

ADCcalPar	4.957 0.19 10000.0
InjCap	7.686000000000001
KSenseInA	21134.913
KSenseInD	21446.654
Name	0x2299a
ChipId	15
NfDSLDO	1.2629717939282172
NfASLDO	1.2637859969915861
NfACB	1.2618576213151855
VcalPar	13.365 0.203
IrefTrim	11
KSenseShuntA	21739.0
KSenseShuntD	22059.0
KShuntA	1004.329
KShuntD	997.911