20UPGFC0141676 Chip Configuration

Stage: MODULE/FINAL_WARM

Branch: LP

Config: 6a28935be4d82762eb8e9582

This Revision: 6a28c58066f3d07de10176e1

Latest Revision: 6a28c58066f3d07de10176e1

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	7
SldoTrimD	9

Parameter

ADCcalPar	5.88 0.185 10000.0
InjCap	7.754
KSenseInA	20820.825
KSenseInD	21362.753
Name	0x2296c
ChipId	14
NfDSLDO	1.2634473866879692
NfASLDO	1.263575945494981
NfACB	1.2617332692611454
VcalPar	13.438 0.198
IrefTrim	5

KSenseShuntA	21416.0
KSenseShuntD	21973.0
KShuntA	1010.233
KShuntD	999.034

PixelConfig

Diff from previous revision 6a28935be4d82762eb8e9583

No diff is present.