20UPGFC0146089 Chip Configuration

Stage: MODULE/FINAL_WARM

Branch: LP

Config: 6a2891f31b95443ad3794b87

This Revision: 6a2891f31b95443ad3794b88

Latest Revision: 6a28c4f166f3d07de10176c4

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	12
SldoTrimD	9

Parameter

ADCcalPar	1.851 0.185 10000.0
InjCap	7.660000000000001
KSenseInA	21084.696
KSenseInD	21294.404
Name	0x23aa9
ChipId	14
NfDSLDO	1.2580277361396643
NfASLDO	1.2578991764754741
NfACB	1.2566707174620984
VcalPar	14.331 0.198
IrefTrim	7

KSenseShuntA	21687.0
KSenseShuntD	21903.0
KShuntA	1001.768
KShuntD	986.918

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	12
SldoTrimD	9

Parameter

ADCcalPar	1.851 0.185 10000.0
InjCap	7.660000000000001
KSenseInA	21084.696
KSenseInD	21294.404
Name	0x23aa9
ChipId	14
NfDSLDO	1.2580277361396643
NfASLDO	1.2578991764754741
NfACB	1.2566707174620984
VcalPar	14.331 0.198
IrefTrim	7
KSenseShuntA	21687.0
KSenseShuntD	21903.0
KShuntA	1001.768
KShuntD	986.918