20UPGFC0146117 Chip Configuration

Stage: MODULE/FINAL_WARM

Branch: LP

Config: 6a2891e31b95443ad3794b7a

This Revision: 6a28cc2066f3d07de10177f4

Latest Revision: 6a28cc2066f3d07de10177f4

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	10
SldoTrimD	9

Parameter

ADCcalPar	2.94 0.183 10000.0
InjCap	7.962999999999999
KSenseInA	21102.97
KSenseInD	21379.594
Name	0x23ac5
ChipId	13
NfDSLDO	1.2571379118510102
NfASLDO	1.2576807175124318
NfACB	1.2572807554461214
VcalPar	16.868 0.198
IrefTrim	8

KSenseShuntA	21706.0
KSenseShuntD	21990.0
KShuntA	999.845
KShuntD	991.518

PixelConfig

Diff from previous revision 6a2891e31b95443ad3794b7b

No diff is present.