20UPGFC0146119 Chip Configuration

Stage: MODULE/FINAL_WARM

Branch: LP

Config: 6a2890f73b97c76890e923c2

This Revision: 6a28c6f8382a2f15c9189c8d

Latest Revision: 6a28c6f8382a2f15c9189c8d

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	7
SldoTrimD	7

Parameter

ADCcalPar	-1.0 0.189 10000.0
InjCap	7.876000000000001
KSenseInA	20981.614
KSenseInD	21312.545
Name	0x23ac7
ChipId	15
NfDSLDO	1.258770525310543
NfASLDO	1.2592561951530405
NfACB	1.2580991581753258
VcalPar	13.48 0.201
IrefTrim	7

KSenseShuntA	21581.0
KSenseShuntD	21921.0
KShuntA	1002.724
KShuntD	991.285

PixelConfig

Diff from previous revision 6a2890f73b97c76890e923c3

No diff is present.