20UPGFC0145956 Chip Configuration

Stage: MODULE/QC_CROSSCHECK

Branch: LP

Config: 6a1f3b5b3728ff7b06582946

This Revision: 6a1f3b5b3728ff7b06582947

Latest Revision: 6a21f5cdae36c5cf13f73d6d

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA9
SldoTrimD10

Parameter

ADCcalPar
  • 6.266
  • 0.189
  • 10000.0
InjCap8.479
KSenseInA21182.206
KSenseInD21629.595
Name0x23a24
ChipId12
NfDSLDO1.252603837360154
NfASLDO1.2536894559214427
NfACB1.251275383068051
VcalPar
  • 12.353
  • 0.204
IrefTrim9
KSenseShuntA21787.0
KSenseShuntD22248.0
KShuntA1008.881
KShuntD987.91

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA9
SldoTrimD10
Parameter
ADCcalPar
  • 6.266
  • 0.189
  • 10000.0
InjCap8.479
KSenseInA21182.206
KSenseInD21629.595
Name0x23a24
ChipId12
NfDSLDO1.252603837360154
NfASLDO1.2536894559214427
NfACB1.251275383068051
VcalPar
  • 12.353
  • 0.204
IrefTrim9
KSenseShuntA21787.0
KSenseShuntD22248.0
KShuntA1008.881
KShuntD987.91