20UPGFC0146023 Chip Configuration

Stage: MODULE/QC_CROSSCHECK

Branch: LP

Config: 6a1f36823728ff7b06582933

This Revision: 6a1f36823728ff7b06582934

Latest Revision: 6a220603ea67888fefd1a07c

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA7
SldoTrimD6

Parameter

ADCcalPar
  • -1.0
  • 0.194
  • 10000.0
InjCap7.642
KSenseInA21034.467
KSenseInD21428.686
Name0x23a67
ChipId15
NfDSLDO1.261853414590263
NfASLDO1.2629390150556166
NfACB1.260639256175065
VcalPar
  • 13.437
  • 0.207
IrefTrim9
KSenseShuntA21635.0
KSenseShuntD22041.0
KShuntA1008.782
KShuntD995.102

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA7
SldoTrimD6
Parameter
ADCcalPar
  • -1.0
  • 0.194
  • 10000.0
InjCap7.642
KSenseInA21034.467
KSenseInD21428.686
Name0x23a67
ChipId15
NfDSLDO1.261853414590263
NfASLDO1.2629390150556166
NfACB1.260639256175065
VcalPar
  • 13.437
  • 0.207
IrefTrim9
KSenseShuntA21635.0
KSenseShuntD22041.0
KShuntA1008.782
KShuntD995.102