20UPGFC0083159 Chip Configuration

Stage: MODULE/WIREBONDING

Branch: LP

Config: 6a161376bf590b6a4c3def83

This Revision: 6a161376bf590b6a4c3def84

Latest Revision: 6a161376bf590b6a4c3def84

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	9
SldoTrimD	10

Parameter

ADCcalPar	14.25 0.183 10000.0
Name	0x144d7
ChipId	14
InjCap	7.871
NfDSLDO	1.2898721654376881
NfASLDO	1.2888960878595423
NfACB	1.2864702479962091
VcalPar	5.068 0.196
IrefTrim	9
KSenseInA	21229.98
KSenseInD	21592.014

KSenseShuntA	26284.737142857142
KSenseShuntD	26732.969714285715
KShuntA	1051.437
KShuntD	1028.028

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	9
SldoTrimD	10

Parameter

ADCcalPar	14.25 0.183 10000.0
Name	0x144d7
ChipId	14
InjCap	7.871
NfDSLDO	1.2898721654376881
NfASLDO	1.2888960878595423
NfACB	1.2864702479962091
VcalPar	5.068 0.196
IrefTrim	9
KSenseInA	21229.98
KSenseInD	21592.014
KSenseShuntA	26284.737142857142
KSenseShuntD	26732.969714285715
KShuntA	1051.437
KShuntD	1028.028