20UPGFC0083142 Chip Configuration

Stage: MODULE/WIREBONDING

Branch: LP

Config: 6a161376bf590b6a4c3def81

This Revision: 6a161376bf590b6a4c3def82

Latest Revision: 6a161376bf590b6a4c3def82

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	13
SldoTrimD	9

Parameter

ADCcalPar	11.964 0.19 10000.0
Name	0x144c6
ChipId	13
InjCap	7.904000000000001
NfDSLDO	1.289067411814292
NfASLDO	1.2881349993445554
NfACB	1.2864136224773495
VcalPar	2.646 0.203
IrefTrim	7
KSenseInA	21297.076
KSenseInD	21749.24

KSenseShuntA	26367.80838095238
KSenseShuntD	26927.630476190476
KShuntA	1056.751
KShuntD	1048.384

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	13
SldoTrimD	9

Parameter

ADCcalPar	11.964 0.19 10000.0
Name	0x144c6
ChipId	13
InjCap	7.904000000000001
NfDSLDO	1.289067411814292
NfASLDO	1.2881349993445554
NfACB	1.2864136224773495
VcalPar	2.646 0.203
IrefTrim	7
KSenseInA	21297.076
KSenseInD	21749.24
KSenseShuntA	26367.80838095238
KSenseShuntD	26927.630476190476
KShuntA	1056.751
KShuntD	1048.384