20UPGFC0223193 Chip Configuration

Stage: MODULE/POST_PARYLENE_COLD

Branch: LP

Config: 6a15ea3408544d4de2d955ef

This Revision: None

Latest Revision: 6a15ea3408544d4de2d955f0

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	10
SldoTrimD	10

Parameter

ADCcalPar	0.089 0.185 10000.0
InjCap	7.5
KSenseInA	20648.292
KSenseInD	21680.93
Name	0x367d9
ChipId	15
NfDSLDO	1.2542935845990764
NfASLDO	1.2547221196703449
NfACB	1.2535793594802946
VcalPar	11.449 0.197
IrefTrim	10

KSenseShuntA	21238.0
KSenseShuntD	22300.0
KShuntA	1007.007
KShuntD	974.141

PixelConfig

Diff from previous revision None

No diff is present.