20UPGFC0223172 Chip Configuration

Stage: MODULE/POST_PARYLENE_COLD

Branch: LP

Config: 6a15ea3008544d4de2d955e2

This Revision: 6a15ea3008544d4de2d955e3

Latest Revision: 6a15ea3008544d4de2d955e3

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	11
SldoTrimD	10

Parameter

ADCcalPar	2.357 0.186 10000.0
InjCap	7.5
KSenseInA	21476.441
KSenseInD	21466.587
Name	0x367c4
ChipId	14
NfDSLDO	1.253440693205066
NfASLDO	1.254412042604915
NfACB	1.2529693030551392
VcalPar	11.887 0.198
IrefTrim	7

KSenseShuntA	22090.0
KSenseShuntD	22080.0
KShuntA	1006.62
KShuntD	972.827

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	11
SldoTrimD	10

Parameter

ADCcalPar	2.357 0.186 10000.0
InjCap	7.5
KSenseInA	21476.441
KSenseInD	21466.587
Name	0x367c4
ChipId	14
NfDSLDO	1.253440693205066
NfASLDO	1.254412042604915
NfACB	1.2529693030551392
VcalPar	11.887 0.198
IrefTrim	7
KSenseShuntA	22090.0
KSenseShuntD	22080.0
KShuntA	1006.62
KShuntD	972.827