20UPGFC0223190 Chip Configuration

Stage: MODULE/POST_PARYLENE_COLD

Branch: LP

Config: 6a15ea2908544d4de2d955c8

This Revision: 6a15ea2908544d4de2d955c9

Latest Revision: 6a15ea2908544d4de2d955c9

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA11
SldoTrimD9

Parameter

ADCcalPar
  • 3.9830000000000005
  • 0.191
  • 10000.0
InjCap7.5
KSenseInA21062.03
KSenseInD21045.906
Name0x367d6
ChipId12
NfDSLDO1.254140636154957
NfASLDO1.2546263108548814
NfACB1.253369270455077
VcalPar
  • 12.103
  • 0.204
IrefTrim10
KSenseShuntA21664.0
KSenseShuntD21647.0
KShuntA993.998
KShuntD980.177

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA11
SldoTrimD9
Parameter
ADCcalPar
  • 3.9830000000000005
  • 0.191
  • 10000.0
InjCap7.5
KSenseInA21062.03
KSenseInD21045.906
Name0x367d6
ChipId12
NfDSLDO1.254140636154957
NfASLDO1.2546263108548814
NfACB1.253369270455077
VcalPar
  • 12.103
  • 0.204
IrefTrim10
KSenseShuntA21664.0
KSenseShuntD21647.0
KShuntA993.998
KShuntD980.177