20UPGFC0222565 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 6a15e9b2bf590b6a4c3d7123

This Revision: 6a15e9b2bf590b6a4c3d7124

Latest Revision: 6a15e9b2bf590b6a4c3d7124

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA9
SldoTrimD9

Parameter

ADCcalPar
  • 0.22
  • 0.187
  • 10000.0
InjCap7.5
KSenseInA21473.264
KSenseInD21373.784
Name0x36565
ChipId15
NfDSLDO1.256979071045694
NfASLDO1.2578647101929832
NfACB1.2563505529411667
VcalPar
  • 12.035
  • 0.199
IrefTrim14
KSenseShuntA22087.0
KSenseShuntD21984.0
KShuntA984.149
KShuntD984.143

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA9
SldoTrimD9
Parameter
ADCcalPar
  • 0.22
  • 0.187
  • 10000.0
InjCap7.5
KSenseInA21473.264
KSenseInD21373.784
Name0x36565
ChipId15
NfDSLDO1.256979071045694
NfASLDO1.2578647101929832
NfACB1.2563505529411667
VcalPar
  • 12.035
  • 0.199
IrefTrim14
KSenseShuntA22087.0
KSenseShuntD21984.0
KShuntA984.149
KShuntD984.143