20UPGFC0222564 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 6a15e9abbf590b6a4c3d7109

This Revision: 6a15e9abbf590b6a4c3d710a

Latest Revision: 6a15e9abbf590b6a4c3d710a

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA9
SldoTrimD8

Parameter

ADCcalPar
  • 0.359
  • 0.18
  • 10000.0
InjCap7.5
KSenseInA21032.334
KSenseInD21639.871
Name0x36564
ChipId13
NfDSLDO1.2568891737862922
NfASLDO1.2575605431597205
NfACB1.2563749334151553
VcalPar
  • 14.998
  • 0.192
IrefTrim9
KSenseShuntA21633.0
KSenseShuntD22258.0
KShuntA1002.693
KShuntD1000.523

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA9
SldoTrimD8
Parameter
ADCcalPar
  • 0.359
  • 0.18
  • 10000.0
InjCap7.5
KSenseInA21032.334
KSenseInD21639.871
Name0x36564
ChipId13
NfDSLDO1.2568891737862922
NfASLDO1.2575605431597205
NfACB1.2563749334151553
VcalPar
  • 14.998
  • 0.192
IrefTrim9
KSenseShuntA21633.0
KSenseShuntD22258.0
KShuntA1002.693
KShuntD1000.523