20UPGFC0222563 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 6a15e9a8bf590b6a4c3d70fc

This Revision: 6a15e9a8bf590b6a4c3d70fd

Latest Revision: 6a15e9a8bf590b6a4c3d70fd

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA8
SldoTrimD8

Parameter

ADCcalPar
  • 7.704
  • 0.182
  • 10000.0
InjCap7.5
KSenseInA21222.023
KSenseInD21405.046
Name0x36563
ChipId12
NfDSLDO1.2573504681074605
NfASLDO1.2578789946953586
NfACB1.2566933809981815
VcalPar
  • 12.895
  • 0.196
IrefTrim7
KSenseShuntA21828.0
KSenseShuntD22017.0
KShuntA985.086
KShuntD985.38

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA8
SldoTrimD8
Parameter
ADCcalPar
  • 7.704
  • 0.182
  • 10000.0
InjCap7.5
KSenseInA21222.023
KSenseInD21405.046
Name0x36563
ChipId12
NfDSLDO1.2573504681074605
NfASLDO1.2578789946953586
NfACB1.2566933809981815
VcalPar
  • 12.895
  • 0.196
IrefTrim7
KSenseShuntA21828.0
KSenseShuntD22017.0
KShuntA985.086
KShuntD985.38