20UPGFC0146119 Chip Configuration

Stage: MODULE/LONG_TERM_STABILITY_TEST

Branch: LP

Config: 6a15e955bf590b6a4c3d70e9

This Revision: 6a15e955bf590b6a4c3d70ea

Latest Revision: 6a15e955bf590b6a4c3d70ea

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA7
SldoTrimD7

Parameter

ADCcalPar
  • -1.0
  • 0.189
  • 10000.0
InjCap7.876000000000001
KSenseInA20981.614
KSenseInD21312.545
Name0x23ac7
ChipId15
NfDSLDO1.258770525310543
NfASLDO1.2592561951530405
NfACB1.2580991581753258
VcalPar
  • 13.48
  • 0.201
IrefTrim7
KSenseShuntA21581.0
KSenseShuntD21921.0
KShuntA1002.724
KShuntD991.285

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA7
SldoTrimD7
Parameter
ADCcalPar
  • -1.0
  • 0.189
  • 10000.0
InjCap7.876000000000001
KSenseInA20981.614
KSenseInD21312.545
Name0x23ac7
ChipId15
NfDSLDO1.258770525310543
NfASLDO1.2592561951530405
NfACB1.2580991581753258
VcalPar
  • 13.48
  • 0.201
IrefTrim7
KSenseShuntA21581.0
KSenseShuntD21921.0
KShuntA1002.724
KShuntD991.285