20UPGFC0146089 Chip Configuration

Stage: MODULE/LONG_TERM_STABILITY_TEST

Branch: LP

Config: 6a15e84fbf590b6a4c3d6cf0

This Revision: 6a15e84fbf590b6a4c3d6cf1

Latest Revision: 6a15e84fbf590b6a4c3d6cf1

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA12
SldoTrimD9

Parameter

ADCcalPar
  • 1.851
  • 0.185
  • 10000.0
InjCap7.660000000000001
KSenseInA21084.696
KSenseInD21294.404
Name0x23aa9
ChipId14
NfDSLDO1.2580277361396643
NfASLDO1.2578991764754741
NfACB1.2566707174620984
VcalPar
  • 14.331
  • 0.198
IrefTrim7
KSenseShuntA21687.0
KSenseShuntD21903.0
KShuntA1001.768
KShuntD986.918

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA12
SldoTrimD9
Parameter
ADCcalPar
  • 1.851
  • 0.185
  • 10000.0
InjCap7.660000000000001
KSenseInA21084.696
KSenseInD21294.404
Name0x23aa9
ChipId14
NfDSLDO1.2580277361396643
NfASLDO1.2578991764754741
NfACB1.2566707174620984
VcalPar
  • 14.331
  • 0.198
IrefTrim7
KSenseShuntA21687.0
KSenseShuntD21903.0
KShuntA1001.768
KShuntD986.918