20UPGFC0146025 Chip Configuration

Stage: MODULE/THERMAL_CYCLES

Branch: LP

Config: 6a15e83fbf590b6a4c3d6cba

This Revision: 6a15e83fbf590b6a4c3d6cbb

Latest Revision: 6a15e83fbf590b6a4c3d6cbb

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA10
SldoTrimD8

Parameter

ADCcalPar
  • 0.001
  • 0.185
  • 10000.0
InjCap7.68
KSenseInA20878.679
KSenseInD21480.11
Name0x23a69
ChipId14
NfDSLDO1.2610190536666355
NfASLDO1.2611476124736474
NfACB1.2591906617446902
VcalPar
  • 15.516
  • 0.198
IrefTrim5
KSenseShuntA21475.0
KSenseShuntD22094.0
KShuntA1020.636
KShuntD996.253

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA10
SldoTrimD8
Parameter
ADCcalPar
  • 0.001
  • 0.185
  • 10000.0
InjCap7.68
KSenseInA20878.679
KSenseInD21480.11
Name0x23a69
ChipId14
NfDSLDO1.2610190536666355
NfASLDO1.2611476124736474
NfACB1.2591906617446902
VcalPar
  • 15.516
  • 0.198
IrefTrim5
KSenseShuntA21475.0
KSenseShuntD22094.0
KShuntA1020.636
KShuntD996.253