20UPGFC0141610 Chip Configuration

Stage: MODULE/QC_STATUS

Branch: LP

Config: 6a0667b65857bb4fa13d616f

This Revision: 6a0667b65857bb4fa13d6170

Latest Revision: 6a074c7a8d85d0e79d6cd9b2

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA10
SldoTrimD8

Parameter

ADCcalPar
  • 2.065
  • 0.179
  • 10000.0
InjCap7.715
KSenseInA20750.446
KSenseInD21334.037
Name0x2292a
ChipId15
NfDSLDO1.2576176809787354
NfASLDO1.2588604285423155
NfACB1.256474924598432
VcalPar
  • 13.307
  • 0.194
IrefTrim9
KSenseShuntA21343.0
KSenseShuntD21944.0
KShuntA986.89
KShuntD994.273

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA10
SldoTrimD8
Parameter
ADCcalPar
  • 2.065
  • 0.179
  • 10000.0
InjCap7.715
KSenseInA20750.446
KSenseInD21334.037
Name0x2292a
ChipId15
NfDSLDO1.2576176809787354
NfASLDO1.2588604285423155
NfACB1.256474924598432
VcalPar
  • 13.307
  • 0.194
IrefTrim9
KSenseShuntA21343.0
KSenseShuntD21944.0
KShuntA986.89
KShuntD994.273