20UPGFC0146891 Chip Configuration

Stage: MODULE/QC_CROSSCHECK

Branch: LP

Config: 6a063ce98a277601d0304443

This Revision: 6a063ce98a277601d0304444

Latest Revision: 6a063ce98a277601d0304444

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA10
SldoTrimD10

Parameter

ADCcalPar
  • -1.0
  • 0.192
  • 10000.0
InjCap7.829
KSenseInA21337.87
KSenseInD21333.653
Name0x23dcb
ChipId14
NfDSLDO1.2576991947756222
NfASLDO1.2585705436106913
NfACB1.2566135798335691
VcalPar
  • 13.546
  • 0.205
IrefTrim9
KSenseShuntA21948.0
KSenseShuntD21943.0
KShuntA998.885
KShuntD976.338

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA10
SldoTrimD10
Parameter
ADCcalPar
  • -1.0
  • 0.192
  • 10000.0
InjCap7.829
KSenseInA21337.87
KSenseInD21333.653
Name0x23dcb
ChipId14
NfDSLDO1.2576991947756222
NfASLDO1.2585705436106913
NfACB1.2566135798335691
VcalPar
  • 13.546
  • 0.205
IrefTrim9
KSenseShuntA21948.0
KSenseShuntD21943.0
KShuntA998.885
KShuntD976.338