20UPGFC0146775 Chip Configuration

Stage: MODULE/QC_CROSSCHECK

Branch: LP

Config: 6a063cdd8a277601d0304429

This Revision: 6a063cdd8a277601d030442a

Latest Revision: 6a063cdd8a277601d030442a

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA8
SldoTrimD8

Parameter

ADCcalPar
  • 1.548
  • 0.185
  • 10000.0
InjCap7.501000000000001
KSenseInA20553.505
KSenseInD21487.575
Name0x23d57
ChipId12
NfDSLDO1.2616719258796802
NfASLDO1.262714677171364
NfACB1.2611291238374345
VcalPar
  • 15.913
  • 0.199
IrefTrim9
KSenseShuntA21141.0
KSenseShuntD22102.0
KShuntA989.777
KShuntD989.071

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA8
SldoTrimD8
Parameter
ADCcalPar
  • 1.548
  • 0.185
  • 10000.0
InjCap7.501000000000001
KSenseInA20553.505
KSenseInD21487.575
Name0x23d57
ChipId12
NfDSLDO1.2616719258796802
NfASLDO1.262714677171364
NfACB1.2611291238374345
VcalPar
  • 15.913
  • 0.199
IrefTrim9
KSenseShuntA21141.0
KSenseShuntD22102.0
KShuntA989.777
KShuntD989.071