20UPGFC0141755 Chip Configuration

Stage: MODULE/FINAL_COLD

Branch: LP

Config: 6a04ad8f8a277601d0304017

This Revision: 6a04e76b0077847aebf6f9d8

Latest Revision: 6a04e76b0077847aebf6f9d8

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	10
SldoTrimD	10

Parameter

ADCcalPar	4.618 0.183 10000.0
InjCap	7.803999999999999
KSenseInA	21038.052
KSenseInD	21874.797
Name	0x229bb
ChipId	14
NfDSLDO	1.2633516082383296
NfASLDO	1.2633944613168628
NfACB	1.2626231059032647
VcalPar	15.547 0.196
IrefTrim	9

KSenseShuntA	21639.0
KSenseShuntD	22500.0
KShuntA	1003.67
KShuntD	999.342

PixelConfig

Diff from previous revision 6a04ad8f8a277601d0304018

No diff is present.