20UPGFC0141720 Chip Configuration

Stage: MODULE/FINAL_COLD

Branch: LP

Config: 6a04ad8b8a277601d030400a

This Revision: 6a04ad8b8a277601d030400b

Latest Revision: 6a04e7650077847aebf6f9ce

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	9
SldoTrimD	7

Parameter

ADCcalPar	-1.0 0.181 10000.0
InjCap	7.634
KSenseInA	21112.641
KSenseInD	21509.412
Name	0x22998
ChipId	13
NfDSLDO	1.2638363516350726
NfASLDO	1.2639506238444451
NfACB	1.2628079017507188
VcalPar	11.777 0.192
IrefTrim	5

KSenseShuntA	21716.0
KSenseShuntD	22124.0
KShuntA	1007.94
KShuntD	999.995

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	9
SldoTrimD	7

Parameter

ADCcalPar	-1.0 0.181 10000.0
InjCap	7.634
KSenseInA	21112.641
KSenseInD	21509.412
Name	0x22998
ChipId	13
NfDSLDO	1.2638363516350726
NfASLDO	1.2639506238444451
NfACB	1.2628079017507188
VcalPar	11.777 0.192
IrefTrim	5
KSenseShuntA	21716.0
KSenseShuntD	22124.0
KShuntA	1007.94
KShuntD	999.995