20UPGFC0141739 Chip Configuration

Stage: MODULE/FINAL_COLD

Branch: LP

Config: 6a04ac4c5857bb4fa13d5bef

This Revision: 6a04e7595857bb4fa13d5d8b

Latest Revision: 6a04ef160077847aebf6fa03

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	7
SldoTrimD	9

Parameter

ADCcalPar	-1.0 0.187 10000.0
InjCap	7.638
KSenseInA	21031.808
KSenseInD	21753.519
Name	0x229ab
ChipId	14
NfDSLDO	1.2638515608212175
NfASLDO	1.264265807247039
NfACB	1.2627088120603311
VcalPar	13.388 0.199
IrefTrim	10

KSenseShuntA	21633.0
KSenseShuntD	22375.0
KShuntA	985.573
KShuntD	997.799

PixelConfig

Diff from previous revision 6a04ac4c5857bb4fa13d5bf0

No diff is present.