20UPGFC0141739 Chip Configuration

Stage: MODULE/FINAL_WARM

Branch: LP

Config: 6a038d948d85d0e79d6cd09f

This Revision: 6a038d948d85d0e79d6cd0a0

Latest Revision: 6a03b5de5857bb4fa13d58cb

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA7
SldoTrimD9

Parameter

ADCcalPar
  • -1.0
  • 0.187
  • 10000.0
InjCap7.638
KSenseInA21031.808
KSenseInD21753.519
Name0x229ab
ChipId14
NfDSLDO1.2638515608212175
NfASLDO1.264265807247039
NfACB1.2627088120603311
VcalPar
  • 13.388
  • 0.199
IrefTrim10
KSenseShuntA21633.0
KSenseShuntD22375.0
KShuntA985.573
KShuntD997.799

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA7
SldoTrimD9
Parameter
ADCcalPar
  • -1.0
  • 0.187
  • 10000.0
InjCap7.638
KSenseInA21031.808
KSenseInD21753.519
Name0x229ab
ChipId14
NfDSLDO1.2638515608212175
NfASLDO1.264265807247039
NfACB1.2627088120603311
VcalPar
  • 13.388
  • 0.199
IrefTrim10
KSenseShuntA21633.0
KSenseShuntD22375.0
KShuntA985.573
KShuntD997.799