20UPGFC0141704 Chip Configuration

Stage: MODULE/FINAL_WARM

Branch: LP

Config: 6a038d908d85d0e79d6cd092

This Revision: 6a038d908d85d0e79d6cd093

Latest Revision: 6a03b5e95857bb4fa13d58e6

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA7
SldoTrimD5

Parameter

ADCcalPar
  • -1.0
  • 0.196
  • 10000.0
InjCap7.544999999999999
KSenseInA21401.834
KSenseInD21647.984
Name0x22988
ChipId13
NfDSLDO1.264442134190758
NfASLDO1.2651134789446832
NfACB1.2633279875778607
VcalPar
  • 13.601
  • 0.21
IrefTrim10
KSenseShuntA22013.0
KSenseShuntD22266.0
KShuntA1005.837
KShuntD976.127

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA7
SldoTrimD5
Parameter
ADCcalPar
  • -1.0
  • 0.196
  • 10000.0
InjCap7.544999999999999
KSenseInA21401.834
KSenseInD21647.984
Name0x22988
ChipId13
NfDSLDO1.264442134190758
NfASLDO1.2651134789446832
NfACB1.2633279875778607
VcalPar
  • 13.601
  • 0.21
IrefTrim10
KSenseShuntA22013.0
KSenseShuntD22266.0
KShuntA1005.837
KShuntD976.127