20UPGFC0141734 Chip Configuration

Stage: MODULE/QC_CROSSCHECK

Branch: LP

Config: 69fe6d5f09f2fa600e725738

This Revision: None

Latest Revision: 6a0244751f68f7138e53e4d3

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	8
SldoTrimD	7

Parameter

ADCcalPar	4.681 0.178 10000.0
InjCap	7.583
KSenseInA	21456.106
KSenseInD	21605.489
Name	0x229a6
ChipId	12
NfDSLDO	1.2642304495000065
NfASLDO	1.2645018478067935
NfACB	1.2632305610013173
VcalPar	11.807 0.192
IrefTrim	7

KSenseShuntA	22069.0
KSenseShuntD	22223.0
KShuntA	991.54
KShuntD	991.613

PixelConfig

Diff from previous revision None

No diff is present.