20UPGFC0141723 Chip Configuration

Stage: MODULE/FINAL_WARM

Branch: cold

Config: 69f907661d764442f06c7c07

This Revision: 69f907661d764442f06c7c08

Latest Revision: 69f907661d764442f06c7c08

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA11
SldoTrimD6

Parameter

ADCcalPar
  • 3.607
  • 0.19
  • 10000.0
InjCap7.526999999999999
KSenseInA20919.766
KSenseInD21478.901
Name0x2299b
ChipId14
NfDSLDO1.263388600699268
NfASLDO1.2634885918825447
NfACB1.2615601904907825
VcalPar
  • 12.366
  • 0.204
IrefTrim5
KSenseShuntA21517.0
KSenseShuntD22093.0
KShuntA985.872
KShuntD985.563

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA11
SldoTrimD6
Parameter
ADCcalPar
  • 3.607
  • 0.19
  • 10000.0
InjCap7.526999999999999
KSenseInA20919.766
KSenseInD21478.901
Name0x2299b
ChipId14
NfDSLDO1.263388600699268
NfASLDO1.2634885918825447
NfACB1.2615601904907825
VcalPar
  • 12.366
  • 0.204
IrefTrim5
KSenseShuntA21517.0
KSenseShuntD22093.0
KShuntA985.872
KShuntD985.563