20UPGFC0141702 Chip Configuration

Stage: MODULE/FINAL_WARM

Branch: LP

Config: 69f907601d764442f06c7bef

This Revision: 69fa456844923dfd6a4fd4c9

Latest Revision: 69fa456844923dfd6a4fd4c9

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA9
SldoTrimD10

Parameter

ADCcalPar
  • 6.983
  • 0.175
  • 10000.0
InjCap7.666000000000001
KSenseInA21177.102
KSenseInD21542.658
Name0x22986
ChipId12
NfDSLDO1.2646320411827396
NfASLDO1.2655747837672322
NfACB1.2632036433274476
VcalPar
  • 14.38
  • 0.189
IrefTrim8
KSenseShuntA21782.0
KSenseShuntD22158.0
KShuntA1004.117
KShuntD992.041

PixelConfig

Diff from previous revision 69f907601d764442f06c7bf0

No diff is present.