20UPGFC0152600 Chip Configuration

Stage: MODULE/WIREBONDING

Branch: LP

Config: 6984e674df0ea5e52db7fc6f

This Revision: 6984e674df0ea5e52db7fc70

Latest Revision: 6984e674df0ea5e52db7fc70

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	10
SldoTrimD	11

Parameter

ADCcalPar	-1.0 0.184 10000.0
InjCap	7.5
KSenseInA	21493.124
KSenseInD	22070.032
Name	0x25418
ChipId	12
NfDSLDO	1.255990497334025
NfASLDO	1.2576619512818863
NfACB	1.254376187110877
VcalPar	13.11 0.196
IrefTrim	7

KSenseShuntA	22107.0
KSenseShuntD	22701.0
KShuntA	1011.83
KShuntD	982.253

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	10
SldoTrimD	11

Parameter

ADCcalPar	-1.0 0.184 10000.0
InjCap	7.5
KSenseInA	21493.124
KSenseInD	22070.032
Name	0x25418
ChipId	12
NfDSLDO	1.255990497334025
NfASLDO	1.2576619512818863
NfACB	1.254376187110877
VcalPar	13.11 0.196
IrefTrim	7
KSenseShuntA	22107.0
KSenseShuntD	22701.0
KShuntA	1011.83
KShuntD	982.253