20UPGFC0141785 Chip Configuration

Stage: MODULE/QC_CROSSCHECK

Branch: LP

Config: 692781ff4186f2811c160446

This Revision: 692781ff4186f2811c160447

Latest Revision: 692781ff4186f2811c160447

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	7
SldoTrimD	7

Parameter

ADCcalPar	0.776 0.186 10000.0
InjCap	7.805
KSenseInA	21248.113
KSenseInD	21461.871
Name	0x229d9
ChipId	15
NfDSLDO	1.261621534317773
NfASLDO	1.261621534317773
NfACB	1.2599216785350733
VcalPar	14.836 0.198
IrefTrim	10

KSenseShuntA	21855.0
KSenseShuntD	22075.0
KShuntA	1006.634
KShuntD	973.957

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	7
SldoTrimD	7

Parameter

ADCcalPar	0.776 0.186 10000.0
InjCap	7.805
KSenseInA	21248.113
KSenseInD	21461.871
Name	0x229d9
ChipId	15
NfDSLDO	1.261621534317773
NfASLDO	1.261621534317773
NfACB	1.2599216785350733
VcalPar	14.836 0.198
IrefTrim	10
KSenseShuntA	21855.0
KSenseShuntD	22075.0
KShuntA	1006.634
KShuntD	973.957