20UPGFC0141672 Chip Configuration

Stage: MODULE/QC_CROSSCHECK

Branch: LP

Config: 692781ed4186f2811c16042c

This Revision: 692781ed4186f2811c16042d

Latest Revision: 692781ed4186f2811c16042d

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	7
SldoTrimD	7

Parameter

ADCcalPar	-1.0 0.184 10000.0
InjCap	7.625000000000001
KSenseInA	21286.041
KSenseInD	21553.413
Name	0x22968
ChipId	13
NfDSLDO	1.2637649315042145
NfASLDO	1.2645791209959947
NfACB	1.262765049672204
VcalPar	12.308 0.195
IrefTrim	7

KSenseShuntA	21894.0
KSenseShuntD	22169.0
KShuntA	1019.687
KShuntD	984.674

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	7
SldoTrimD	7

Parameter

ADCcalPar	-1.0 0.184 10000.0
InjCap	7.625000000000001
KSenseInA	21286.041
KSenseInD	21553.413
Name	0x22968
ChipId	13
NfDSLDO	1.2637649315042145
NfASLDO	1.2645791209959947
NfACB	1.262765049672204
VcalPar	12.308 0.195
IrefTrim	7
KSenseShuntA	21894.0
KSenseShuntD	22169.0
KShuntA	1019.687
KShuntD	984.674