20UPGFC0141702 Chip Configuration

Stage: MODULE/QC_CROSSCHECK

Branch: LP

Config: 692781dd4186f2811c16041f

This Revision: 692781dd4186f2811c160420

Latest Revision: 692781dd4186f2811c160420

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	9
SldoTrimD	10

Parameter

ADCcalPar	6.983 0.175 10000.0
InjCap	7.666000000000001
KSenseInA	21177.102
KSenseInD	21542.658
Name	0x22986
ChipId	12
NfDSLDO	1.2646320411827396
NfASLDO	1.2655747837672322
NfACB	1.2632036433274476
VcalPar	14.38 0.189
IrefTrim	8

KSenseShuntA	21782.0
KSenseShuntD	22158.0
KShuntA	1004.117
KShuntD	992.041

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	9
SldoTrimD	10

Parameter

ADCcalPar	6.983 0.175 10000.0
InjCap	7.666000000000001
KSenseInA	21177.102
KSenseInD	21542.658
Name	0x22986
ChipId	12
NfDSLDO	1.2646320411827396
NfASLDO	1.2655747837672322
NfACB	1.2632036433274476
VcalPar	14.38 0.189
IrefTrim	8
KSenseShuntA	21782.0
KSenseShuntD	22158.0
KShuntA	1004.117
KShuntD	992.041