20UPGFC0141620 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 690279aae51e26cf8a948aa0

This Revision: 690abe183d2fe659a499327e

Latest Revision: 6920c7e4debdf73f4322bd82

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	8
SldoTrimD	8

Parameter

ADCcalPar	-1.0 0.19 10000.0
InjCap	7.807999999999999
KSenseInA	20927.22
KSenseInD	22000.258
Name	0x22934
ChipId	15
NfDSLDO	1.2621861593933874
NfASLDO	1.2621004538077694
NfACB	1.2605434690023796
VcalPar	13.793 0.203
IrefTrim	6

KSenseShuntA	21525.0
KSenseShuntD	22629.0
KShuntA	989.095
KShuntD	991.101

PixelConfig

Diff from previous revision 6902eb7760809c59eae8ce2e

No diff is present.