20UPGFC0141732 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 690279a6e51e26cf8a948a93

This Revision: 690279a6e51e26cf8a948a94

Latest Revision: 6920c7d6debdf73f4322bd79

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	5
SldoTrimD	7

Parameter

ADCcalPar	-1.0 0.19 10000.0
InjCap	7.861000000000001
KSenseInA	21339.063
KSenseInD	21457.723
Name	0x229a4
ChipId	14
NfDSLDO	1.2643187297132712
NfASLDO	1.2643901512727225
NfACB	1.2632045533858363
VcalPar	13.186 0.203
IrefTrim	14

KSenseShuntA	21949.0
KSenseShuntD	22071.0
KShuntA	1000.936
KShuntD	957.621

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	5
SldoTrimD	7

Parameter

ADCcalPar	-1.0 0.19 10000.0
InjCap	7.861000000000001
KSenseInA	21339.063
KSenseInD	21457.723
Name	0x229a4
ChipId	14
NfDSLDO	1.2643187297132712
NfASLDO	1.2643901512727225
NfACB	1.2632045533858363
VcalPar	13.186 0.203
IrefTrim	14
KSenseShuntA	21949.0
KSenseShuntD	22071.0
KShuntA	1000.936
KShuntD	957.621