20UPGFC0141635 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 690279a2e51e26cf8a948a86

This Revision: 690abe113d2fe659a499326c

Latest Revision: 6920c7d2debdf73f4322bd70

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	8
SldoTrimD	8

Parameter

ADCcalPar	5.42 0.185 10000.0
InjCap	7.8100000000000005
KSenseInA	21101.771
KSenseInD	21910.698
Name	0x22943
ChipId	13
NfDSLDO	1.2625819096393818
NfASLDO	1.2630247203555127
NfACB	1.2613106143575863
VcalPar	11.185 0.197
IrefTrim	8

KSenseShuntA	21705.0
KSenseShuntD	22537.0
KShuntA	986.273
KShuntD	983.563

PixelConfig

Diff from previous revision 6902eb7160809c59eae8ce1c

No diff is present.