20UPGFC0141634 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 6902799fe51e26cf8a948a79

This Revision: 6920c7c6debdf73f4322bd67

Latest Revision: 6920c7c6debdf73f4322bd67

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	6
SldoTrimD	6

Parameter

ADCcalPar	1.728 0.184 10000.0
InjCap	8.734
KSenseInA	20982.013
KSenseInD	21592.734
Name	0x22942
ChipId	12
NfDSLDO	1.261646689665179
NfASLDO	1.261518133858203
NfACB	1.2608753548233218
VcalPar	13.583 0.197
IrefTrim	15

KSenseShuntA	21581.0
KSenseShuntD	22210.0
KShuntA	994.934
KShuntD	991.033

PixelConfig

Diff from previous revision 691f5240a41f3148e9de6525

No diff is present.