20UPGFC0142478 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68db0898fc2f5b6275d41c82

This Revision: 6902eb4b1f6a7995c5f69ae3

Latest Revision: 6920d5b2948273b4430bad4f

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	9
SldoTrimD	7

Parameter

ADCcalPar	0.104 0.189 10000.0
InjCap	7.891
KSenseInA	21157.859
KSenseInD	21373.947
Name	0x22c8e
ChipId	14
NfDSLDO	1.2577521393099869
NfASLDO	1.258709191397229
NfACB	1.2567522341442112
VcalPar	13.046 0.203
IrefTrim	5

KSenseShuntA	21762.0
KSenseShuntD	21985.0
KShuntA	1003.441
KShuntD	985.725

PixelConfig

Diff from previous revision 69017e39aa4113d5eec4d497

No diff is present.