20UPGFC0142507 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68db0885fc2f5b6275d41c74

This Revision: 6902eb481f6a7995c5f69ada

Latest Revision: 694341671402cc2a2d46eda1

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	12
SldoTrimD	8

Parameter

ADCcalPar	-1.0 0.189 10000.0
InjCap	7.708
KSenseInA	20984.324
KSenseInD	21706.826
Name	0x22cab
ChipId	13
NfDSLDO	1.2592763676160317
NfASLDO	1.259090671561459
NfACB	1.2572337110157332
VcalPar	13.261 0.201
IrefTrim	6

KSenseShuntA	21584.0
KSenseShuntD	22327.0
KShuntA	986.224
KShuntD	988.617

PixelConfig

Diff from previous revision 69017e35aa4113d5eec4d48e

No diff is present.