20UPGFC0142490 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68db0878fc2f5b6275d41c67

This Revision: 694341641402cc2a2d46ed98

Latest Revision: 694341641402cc2a2d46ed98

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	1
SerSelOut3	3
SldoTrimA	9
SldoTrimD	10

Parameter

ADCcalPar	0.815 0.186 10000.0
InjCap	7.726999999999999
KSenseInA	20954.814
KSenseInD	21734.08
Name	0x22c9a
ChipId	12
NfDSLDO	1.258113442582458
NfASLDO	1.2585276903892944
NfACB	1.2570992496760665
VcalPar	13.358 0.199
IrefTrim	10

KSenseShuntA	21554.0
KSenseShuntD	22355.0
KShuntA	1001.803
KShuntD	1001.044

PixelConfig

Diff from previous revision 6920d5aa948273b4430bad2b

No diff is present.