20UPGFC0142478 Chip Configuration

Stage: MODULE/INITIAL_COLD

Branch: LP

Config: 68dafc62fc2f5b6275d41bb7

This Revision: 68dafc62fc2f5b6275d41bb8

Latest Revision: 68dafc62fc2f5b6275d41bb8

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA9
SldoTrimD7

Parameter

ADCcalPar
  • 0.104
  • 0.189
  • 10000.0
InjCap7.891
KSenseInA21157.859
KSenseInD21373.947
Name0x22c8e
ChipId14
NfDSLDO1.2577521393099869
NfASLDO1.258709191397229
NfACB1.2567522341442112
VcalPar
  • 13.046
  • 0.203
IrefTrim5
KSenseShuntA21762.0
KSenseShuntD21985.0
KShuntA1003.441
KShuntD985.725

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA9
SldoTrimD7
Parameter
ADCcalPar
  • 0.104
  • 0.189
  • 10000.0
InjCap7.891
KSenseInA21157.859
KSenseInD21373.947
Name0x22c8e
ChipId14
NfDSLDO1.2577521393099869
NfASLDO1.258709191397229
NfACB1.2567522341442112
VcalPar
  • 13.046
  • 0.203
IrefTrim5
KSenseShuntA21762.0
KSenseShuntD21985.0
KShuntA1003.441
KShuntD985.725