20UPGFC0142220 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68dafbc0fc2f5b6275d41b61

This Revision: 68dafbd8fc2f5b6275d41b8b

Latest Revision: 68dafbd8fc2f5b6275d41b8b

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	7
SldoTrimD	6

Parameter

ADCcalPar	3.894 0.188 10000.0
InjCap	7.709999999999999
KSenseInA	21064.906
KSenseInD	21993.453
Name	0x22b8c
ChipId	15
NfDSLDO	1.2617265219934586
NfASLDO	1.2615979653293437
NfACB	1.2603409668357748
VcalPar	11.901 0.2
IrefTrim	10

KSenseShuntA	21667.0
KSenseShuntD	22622.0
KShuntA	1013.392
KShuntD	984.498

PixelConfig

Diff from previous revision 68dafbc0fc2f5b6275d41b62

No diff is present.