20UPGFC0142182 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68dafbbbfc2f5b6275d41b54

This Revision: 68dafbbbfc2f5b6275d41b55

Latest Revision: 68dafbd1fc2f5b6275d41b80

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	10
SldoTrimD	11

Parameter

ADCcalPar	2.941 0.178 10000.0
InjCap	7.634
KSenseInA	21145.98
KSenseInD	21712.558
Name	0x22b66
ChipId	14
NfDSLDO	1.2611005553088952
NfASLDO	1.2617147786724892
NfACB	1.260400626359683
VcalPar	14.848 0.191
IrefTrim	7

KSenseShuntA	21750.0
KSenseShuntD	22333.0
KShuntA	994.506
KShuntD	989.539

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	10
SldoTrimD	11

Parameter

ADCcalPar	2.941 0.178 10000.0
InjCap	7.634
KSenseInA	21145.98
KSenseInD	21712.558
Name	0x22b66
ChipId	14
NfDSLDO	1.2611005553088952
NfASLDO	1.2617147786724892
NfACB	1.260400626359683
VcalPar	14.848 0.191
IrefTrim	7
KSenseShuntA	21750.0
KSenseShuntD	22333.0
KShuntA	994.506
KShuntD	989.539