20UPGFC0142412 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68dafbb65dcff4364d6a2b1b

This Revision: 6902dc2b96387c76c66daa1d

Latest Revision: 6920d5bd948273b4430bad6d

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	11
SldoTrimD	11

Parameter

ADCcalPar	3.846 0.185 10000.0
InjCap	7.894000000000001
KSenseInA	21119.058
KSenseInD	21898.571
Name	0x22c4c
ChipId	15
NfDSLDO	1.2577336619318904
NfASLDO	1.2579907795459138
NfACB	1.2570337306492707
VcalPar	11.823 0.198
IrefTrim	4

KSenseShuntA	21722.0
KSenseShuntD	22524.0
KShuntA	990.202
KShuntD	989.392

PixelConfig

Diff from previous revision 6901783daa4113d5eec4d431

No diff is present.