20UPGFC0142445 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 68dafbb15dcff4364d6a2b0e

This Revision: 6902dc2796387c76c66daa14

Latest Revision: 6920d5b5948273b4430bad58

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	8
SldoTrimD	10

Parameter

ADCcalPar	4.225 0.183 10000.0
InjCap	7.933
KSenseInA	21324.717
KSenseInD	21374.64
Name	0x22c6d
ChipId	14
NfDSLDO	1.2585192990858511
NfASLDO	1.257933642298353
NfACB	1.2567908973471371
VcalPar	13.65 0.198
IrefTrim	7

KSenseShuntA	21934.0
KSenseShuntD	21985.0
KShuntA	997.71
KShuntD	975.014

PixelConfig

Diff from previous revision 6901783aaa4113d5eec4d428

No diff is present.